Date: Sunday 1 June 2014
Time: Morning 0900 – 1200 / Afternoon 1330 – 1630
Venue: Melbourne Convention Centre
Cost: Included in full symposium registration fee OR
Full Day $AUD290.00 / Half Day $AUD180.00 inc GST for tutorial only (no full symposium registration)
Tutorials are included in the full symposium registration fee and can be booked via the online registration form. A registration fee applies to anyone wishing to attend a tutorial with no symposium registration. Registration for a tutorial only is available via the online registration form by clicking the button below. Select ‘new registration’, enter your demographic details then select ‘tutorial only registration’ (full or half day) on the Registration page. Payment can be made via the online form.
Already registered and want to change or add a tutorial? You may do so by accessing your registration record using the ‘Access Key’ provided in your registration confirmation email. From the menu on the left hand side please click the ‘edit’ button next to Tutorials and proceed to make a selection.
Tutorial Program
| Morning Tutorials (0900 – 1200) | Room |
| T1: Design and Implementation of Next Generation Video Coding Systems | 212 |
| T3: 3D ICs – Challenges and Advantages | 220 |
| T5: Integrated Sensors and Sensor Readouts for Emerging Biomedical Applications | 217 |
| T7: GOLD – Engineering Networks that Work: Design Tools for Your Career | 210 |
| T9: FULL DAY – Recent Advances In Machine Intelligence And Data Mining (continues following lunch) | 219 |
| T10: Principles of Adaptive Filters: Applications, Recent Advances and Problems | 209 |
| T14: Neuromorphic Systems: Towards Deep Submicron and Real World Applications | 211 |
| T16: Class-D: Fundamentals, Design Tradeoffs and Problems | 216 |
| T18: Near‐field Wireless Power and Data Telemetry | 213 |
| T20: Managing Technology Professionals: Transitioning from Individual Contributor to Management | 218 |
| T21: If it’s Pinched it’s a memristor (0900 – 1030) | 208 |
| T22: ReRAM Memristive Devices: Electrochemical Systems at the Atomic Scale (1050 – 1200) | 208 |
Lunch Break (1200 – 1330)
| Afternoon Tutorials (1330 – 1630) | Room |
| T2: Circuit Implementation of Data Telemetry for Implants | 212 |
| T4: Near‐Threshold VLSI Circuits and Systems for Nearly Minimum‐Energy Computing: from Basics to State of the Art | 220 |
| T6: Evolutionary Computation applied to Analog IC Design Automation | 217 |
| T8: Advanced Digital Calibration Techniques for Data Converters | 210 |
| T9: FULL DAY – Recent Advances in Machine Intelligence and Data Mining (continues from morning session) | 219 |
| T11: Nonlinear distortion analysis of circuits and systems | 209 |
| T15: Switching Noise Reduction Techniques in DC-DC Converters for Powering Noise-Sensitive Analog and RF Loads | 216 |
| T17: Small Scale Energy Harvesting (EH) – Principles, Practices, and Future Trends | 213 |
| T19: Interfacing Organisations: How to Successfully Manage Organisational Interfaces | 218 |
| T23: Analog and Mixed-Signal Applications of Memristive Devices (1330 – 1500) | 208 |
| T24: Integrating memristive devices in CMOS neuromorphic computing architectures (1520 – 1630) | 208 |
Tutorial Details
Subject to change and/or cancellation dependant on final numbers.
T1: Design and Implementation of Next Generation Video Coding Systems |
Date: Sunday 1 June 2014 Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 212 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator: Vivienne Sze and Madhukar BudagaviAdvances in video compression, which have enabled us to squeeze more pixels through bandwidth‐constrained channels, have been critical in the rapid growth of video. As we continue to push for higher coding efficiency, higher resolutions and more sophisticated multimedia applications, the required number of computations per pixel and pixel processing rate will grow exponentially. This poses significant power and performance challenges for battery operated devices such as smart phones and tablets, as well as emerging devices such as wearable cameras/displays and video sensors. In order to address these challenges, co–‐design of algorithms and architectures is required for next generation video coding systems.The first part of the tutorial will give a background on video coding and provide an overview of existing video coding systems and their applications, particularly for H.264/AVC which is currently the most widely used video coding standard in the world. It will cover implementations on a variety of platforms including ASIC, FPGA and multi‐core processors. The key challenges in the design and implementation of these systems will be highlighted. The techniques used to improve energy‐ efficiency and performance in the current state‐of‐the‐art implementations and the limitations of these techniques will be described.The second part of the tutorial will then introduce the next generation video coding standard, High Efficiency Video Coding (HEVC), recently standardized in January 2013. It will provide insight on how joint algorithm and architecture design was used in the development of HEVC to overcome various implementation challenges while still enabling a 2x improvement in coding efficiency compared to H.264/AVC. Various implementation-‐friendly features will be highlighted. The impact of co-design will be illustrated through various HEVC encoder and decoder implementations.The final part of the tutorial will provide examples of how video coding can be used a wide variety of emerging applications, and discuss the future directions and challenges that lie ahead. |
T2: Circuit Implementation of Data Telemetry for Implants |
Time: 13:30 - 16:30 Venue: Melbourne Convention Centre Room: 212 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Sherif MohamedPower and data telemetry are mandatory components for all implantable systems. Especially multichannel recorders and stimulators require both large power and high data rates. Nonetheless, in many systems the telemetry is just implemented with a holistic approach, but not analyzed in large detail. Based on the fact that most implantable devices dissipate the largest amount of power in the telemetry subsystem, a careful design or even active adaptability of the link are thought necessary in order to provide high energy-efficiency as well as to meet with regulatory compliance. Still today, most systems use RF data telemetry which suffers from large power consumption. Power delivery is mostly done without feedback control, or batteries are employed. On the emerging side, power efficient data transfer using UWB or non-RF telemetry, such as optical or ultrasonic approaches have shown to be excellent alternatives. Feedback controlled power telemetry or energy harvesting systems have shown high efficiency. This tutorial will give an overview and design guidelines for high-efficiency data and power telemetry for implantable systems. It first reviews the common RF based approaches, and secondly highlights new approaches such as energy harvesting and non-RF communication. Furthermore, it will introduce two working examples for data transmission in implanted medical devices, the 402-405MHz and the 13.56MHz, which are adapted as the in-body devices. A fully monolithic CMOS direct conversion and low-IF receiver architectures with integrated quadrature LO chain, which is implemented in a closed-loop type-II PLL system for 402-405MHz band (MICS applications). This system is designed and implemented in a 0.13-μm CMOS process. And a new approach for wireless efficient wideband data transmission to implantable microelectronic medical devices (RFID) will be presented. |
T3: 3D ICs – Challenges and Advantages |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 220 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Maciej OgorzalekThe most significant challenge for continued integration of complex systems is energy efficiency. 3D heterogeneous stacking of diverse circuit blocks is one of the most promising solutions.The tutorial will focus on three-dimensional integrated circuits (3D lCs) consisting of multiple layers of systems integrated vertically using through silicon vias (TSVs). We will discuss advantages and challenges of current 3D TSV-based technologies and how to exploit various options through tradeoffs and well-educated choices for designing energy efficient heterogeneous systems.Challenging and non-trivial research questions resulting from diverse dependencies will be addressed. Theses will include system types, functionalities, the variety of materials, TSV-based vertical integration technologies, TSV modeling, the system 3D architecture, energy efficiency, technological feasibility, and the multi-objective optimization problems on various levels of abstractions. Comparisons between various TSV models and layout solutions will be presented and discussed. Influence of TSV-induced thermo-mechanical stress on devices and interconnects will be evaluated through comparison of layout optimization results.We will also look towards the horizon, exploring a variety of new materials such as Ill-V semiconductors and carbon-nanotubes and the potential of an abundance of energy efficient interconnects. An overview of current new concepts for construction of heterogeneous layers on chip containing such devices as energy scavengers and energy storing devices including hyper-capacitors and micro-batteries will be presented. |
T4: Near‐Threshold VLSI Circuits and Systems for Nearly Minimum‐Energy Computing: from Basics to State of the Art |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 212 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Massimo AliotoIn the last few years, near‐threshold computing has gained a considerable attention from the industrial and academic community, thanks to the one‐order of magnitude energy/power reduction that it can potentially enable. In particular, near‐threshold circuits promise a more sustainable performance growth over the next CMOS technology generation for constant power envelope, as well as much more functionality on mobile devices.However, near‐threshold circuits typically target 400‐500 mV operation, which poses many challenges that need to be solved, before near‐threshold integrated systems become viable for commercialization. Among those challenges, leakage comes back as crucial issue, since the related percentage of chip power can be easily 4‐5X larger than that observed at nominal voltage (e.g., 1 V). Typically, 10X larger process/voltage/temperature variations challenge the robustness and ultimately the yield of near‐threshold systems, compared to nominal voltage. Moreover, the typical 10X performance degradation compared to nominal voltage requires rethinking architectures, as well as their interaction with circuit (down) and software level (up in the stack). Run‐time techniques to detect/fix functional and soft failures need to be cohesively adopted at all levels of abstraction.In this tutorial, a survey of fresh ideas and very recent techniques to design near‐threshold CMOS logic circuits and systems is presented. Emphasis is given on design solutions, and on the interaction between different levels of abstraction, since the above challenges need to be tackled at all levels of abstraction in a unitary manner. To give a unitary perspective, a few design principles are preliminarily introduced and then further developed for the main building blocks of Systems on Chip (processors, SRAM arrays, on‐chip network and specialized hardware). The impact of sub‐32nm technologies and the key design tradeoffs at near threshold are consistently exemplified by recent industrial and academic prototypes. Then, the tutorial explicitly addresses all key challenges, including energy efficiency, leakage and resiliency. Limits of current techniques to reduce leakage and dynamic energy are discussed, and fine‐grain techniques are introduced as solution to improve the overall energy efficiency. Near‐threshold‐specific design flows are discussed and compared to traditional flows. Promising directions and future work are suggested at the end of the tutorial. |
T5: Integrated Sensors and Sensor Readouts for Emerging Biomedical Applications |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 217 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Jens AndersMany conventional sensor systems consist of a combination of discrete off-the-shelf sensing elements and discrete op-amp-based readout electronics. This configuration frequently leads to a situation where parasitic resistances and capacitances at the interface between sensor and readout electronics become the bottleneck for the achievable speed and/or resolution. In this tutorial, we will discuss the potential of advanced IC and MEMS-based technologies to overcome these limitations and allow for the design of high-speed, high-resolution biochemical sensor systems which thanks to their improved performance can enable new insights into the structure of biological molecules and the dynamics of biochemical processes. More specifically, using three exemplary emerging biomedical analysis modalities (NMR microscopy, ESR spectroscopy and atomic force microscopy) it will explained how a smart codesign of the sensing element together with the sensing electronics in a system-in-package or even inside a single ASIC can result in significantly improved system performance by reducing parasitics associated with interconnects and/or the sensing element itself. Additionally, we will compare advanced signal demodulation concepts (e.g. energy based demodulation using the Teager Energy Operator) with well-established methods such as lock-in detection and show how these methods can overcome existing speed limitations by providing true single-cycle detection. Finally, we will provide a general comparison of classical amplitude-sensitive detection schemes against emerging frequency-sensitive methods and show how despite their intrinsically equivalent sensitivities the two detection schemes display significantly different signal, noise and bandwidth values which render one or the other method favorable for a certain specific sensing application. |
T6: Evolutionary Computation applied to Analog IC Design Automation |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 217 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Nuno HortaIn the last decades, Very Large Scale Integration (VLSI) technologies have been widely improved, allowing the proliferation of consumer electronics and enabling the growth of integrated circuits (IC) market from $10 billion in 1980 to over than $300 billion in 2013, according to IC Insights Inc. The increasing complexity of electronic systems design and the strict time-to-market impose the use of Computer Aided Design (CAD) tools to support the IC design process.Despite of the mature stage of Electronic Design Automation (EDA) tools for digital IC design, analog IC design automation tools struggle to keep up with the new challenges created by deep nanometer technologies. Due to the lack of automation, analog designers still explore the solution space almost manually. This method causes long design times, and allied to the non-reusable nature of analog IC, makes analog IC design a cumbersome task. The use of evolutionary computation (EC) techniques in analog IC design automation is wide spreading. Particularly, the exploration of new topologies and the optimal sizing using evolutionary multi-objective optimization (EMO) approaches, as well as, the placement and routing optimization, at physical level, using EC techniques are application examples in the area of analog IC design automation. The benefits of EC are huge in terms of design time reduction and also in terms of improved IC performance.This tutorial addresses the application of EC to analog IC design automation. First, a brief introduction to the analog IC design automation will be presented. Then, the state-of-the-art on analog IC design automation will be reviewed. Next, the application of EMO techniques to circuit sizing optimization, as well as, the application of EC techniques to automatic layout generation will be discussed, including the presentation of practical examples. Finally, future trends on EC applied to analog IC design automation will be highlighted. |
T7: Engineering Networks that Work: Design Tools for Your Career |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 210 Cost: Free of charge Facilitator/s: Elena Blokhina, Margaret Collins, Pamela Abshire and Yoko UwateSpoiler alert: this tutorial will NOT teach you to design more effective routers or interchip communication protocols. It WILL teach you how to communicate more effectively and build networks of colleagues in order to support your future career development.Meetings like ISCAS are important precisely because they offer so many opportunities for professional growth and development – but do you know how to recognize and gain maximum advantage from the rich array of opportunities before you? We’re all familiar with the stereotype of engineers as antisocial misanthropes who lack the social skills to initiate or maintain conversation. That is a vast generalization, and there are lots of examples to the contrary, but it is true that engineers are often so focused on technical advancement and training that they neglect many simple and easy techniques that they could use to boost their own careers and create more opportunities to realize and develop their technical ideas and projects. This tutorial will operate like a workshop, introducing participants to some of these challenges, presenting strategies to overcome them, and working in small groups to practice some of these strategies. Topics covered will be relevant to: social skills, presentation skills, professional networking, setting up collaborations, maintaining collaborations, impostor syndrome, protecting your core values, volunteerism, pitfalls of technical careers and how to avoid them, workplace culture. Seasoned, successful researchers from the CAS community will be invited to offer short personal stories to complement the program and to offer practical advice on your career issues and questions. |
T8: Advanced Digital Calibration Techniques for Data Converters |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 210 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Yun ChiuThis tutorial identifies the recent trend of data converter design in nanometer CMOS technologies. The focus will be placed on low-power SAR and high-speed pipeline architectures – the two dominant multistep conversion techniques existing these days. Digital calibration techniques enhancing the performance of these converters beyond the raw accuracy level offered by fabrication technology will be covered in detail. Particularly, an important concept of “redundancy” in pipeline ADC and SAR ADC will be analyzed – it will be pointed out that it is redundancy that has been exploited all along to enable all kinds of digital background calibrations of these converters! The commonality and difference between the pipeline and SAR redundancy will also be analyzed, followed by a few case studies that highlight the latest advancement in the conversion accuracy and speed performance of these converters. The low-power aspect of the design, which is claimed as “most critical” in proliferating hand-held devices as well as in large data centers (e.g., Google and Facebook farms) for communication and computing purposes, will be studied in detail. The recent trend of low-power SAR ADC to dominate for 100-200 MS/s, 12-14 bits applications will be pointed out and analyzed. Interestingly, academic and industrial works are heading in two disparate directions as evidenced by recent publications as well as product releases, which is mind-boggling but obviously deserves some attention – the tutorial will conclude by making some observations related to this dichotomy. |
T9: Recent Advances In Machine Intelligence And Data Mining |
Time: 9:00-12:00, 13:30 –16:30 (Full- Day) Venue: Melbourne Convention Centre Room: 219 Cost: Included in full symposium registration fee $AUD290.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Moncef GabboujAs media content is prominent in our everyday life, efficient data mining within this massive source of information through its full life cycle (from creation to consumption by the user) defines the general scope of this tutorial. Multimedia content features (also called descriptors) play a central role in many computer vision and image processing applications. Features are various types of information extracted from the content and represent some of its characteristics or signatures. However, especially the (low-level) features, which can be extracted automatically usually lack the discrimination power needed for accurate processing especially in the case of a large and varied media content data reserves. Therefore, we shall present a recent evolutionary technique, the Multi-Dimensional Particle Swarm Optimization to synthesize highly discriminative features using a novel evolutionary feature synthesis framework. Furthermore, for classifying and indexing a large media content data reserve, the key questions are: 1) how to select certain features so as to achieve the highest discrimination over certain classes, 2) how to combine them in the most effective way, 3) which distance metric to apply, 4) how to find the optimal classifier configuration for the classification problem at hand, and 5) how to scale/adapt the classifier if a large number of classes/features are present and finally, 6) how to train the classifier efficiently to maximize the classification accuracy. In this tutorial recent evolutionary techniques and novel classifier topologies will be introduced to address these questions. |
T10: Principles of Adaptive Filters: Applications, Recent Advances and Open Problems |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 209 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Tokunbo OgunfunmiAdaptive filtering techniques are used in a wide range of applications, including echo cancellation, adaptive equalization, adaptive noise cancellation, and adaptive beamforming to name a few.In this tutorial, we elucidate the underlying principles behind adaptive filters and provide a comprehensive introduction to the area of both linear and non-linear adaptive filter theories.We present recent advances in the field. For applications such as communications, image processing, and biological systems, nonlinear filters are well-suited for modeling the naturally-occurring physical characteristics. There is an interest in understanding methods of nonlinear adaptive filtering. Kernel methods are a powerful new approach which can provide considerable complexity reduction for nonlinear filtering, as well as the potential for universal function approximation. We also present other Machine Learning ideas applied to Adaptive Filtering such as Information-Theoretic learning. These approaches are of particular interest for real-time applications.The use of complex data in adaptive filters is also desirable for some applications. Complex-valued data provides phase as well as magnitude information, allowing for conveying both ‘intensity’ and ‘direction’ of input in a manner naturally suited for these applications. This opens up new areas for research into use of complex-valued data for nonlinear adaptive filtering particularly with kernel-based methods.Quaternions, which are an example of hyper-complex data, provide a convenient representation for performing transformations in 3 or 4-dimensional space. Quaternions are particularly well-suited for robotics applications, specifically image pattern recognition and modeling motion in 3-dimensions. However, the use of quaternions for adaptive filtering has been hampered by the fact that multiplication of quaternions is non-commutative which complicates gradient operations using quaternion-based cost functions.Finally, we discuss application areas, hardware implementations and open research problems.We hope the material presented here will educate new comers to the field and also help elucidate to practicing engineers (involved in both the theory, algorithm and implementation issues) and researchers the important area of adaptive filters. |
T11: Nonlinear distortion analysis of circuits and systems |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 209 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Gerd Vandersteen and Adam CoomanThis tutorial aims to demystify the nonlinear distortion analysis of circuits and systems. Combining capability of analyzing large circuits through simulation-based methods and the analytical insight provided by symbolic methods enables the analysis of the nonlinear behavior of complex systems. The simulation-based methods make it possible to pinpoint the dominant nonlinearities, while the symbolic method can be used afterwards to get an analytical insight in the nonlinear behavior. This will be demonstrated using a large set of practical examples.The tutorial first introduces the necessary notions on Volterra theory, starting from classical linear system theory. The analytical expressions provided by Volterra result in a better understanding of the behavior of the system. The complexity of the resulting expressions, however, limits this technique to simple systems.Second, the tutorial introduces the Best-Linear-Approximation (BLA) paradigm, which represents the nonlinear system as a linear transfer function and additive nonlinear distortion components. It enables the separation of the various linear and nonlinear contributions and is able to pinpoint the dominant nonlinear distortions in a complex system and this in a hierarchical way. The main drawback of the simulation-based methods is, however, the reduced analytical insight.Finally, the power of both methods is illustrated on applications. Starting from a single-transistor circuit (a common source amplifier), the circuits’ complexity gradually increases over OPAMPs (different topologies), sigma-delta modulators and a receiver architecture. Both the symbolic method and the simulation-based methods are used side-by-side to gain insight in the nonlinear distortion properties of the system. All results are finally cross-checked and compared with publication results available in the literature. |
T12: Spintronics and Straintronics – Theory and Applications – CANCELLED |
This tutorial has been cancelled. Apologies for any inconvenience caused.Facilitator/s: Pinaki MazumderAs CMOS continues to scale beyond sub-22 nm feature sizes, non-charge based alternative technologies are being vigorously pursued to meet ravenous demands for higher integration density, faster system throughput, lower power dissipation, and superior circuit noise immunity and system reliability. The viable candidate technology must be compatible with CMOS process technologies and thereby it must be able to sustain the aggressive pace of CMOS device scaling. Spintronics is one such technology that exploits the property of the quantized spin of an electron to meet the above-mentioned objectives. This half-day tutorial will provide the theoretical framework of various types of spintronic devices as they have evolved over the past two decades in the form of i) spin valve, ii) toggle MRAM, iii) in-plane spin-transfer torque (STT), iv) perpendicular STT-RAM, and finally v) straintronics (STR) RAM devices. The tutorial will use physics based modeling techniques to show how the Write current in these spintronics memory (MRAM) devices have been reduced from several mA (spin valve and toggle MRAM) to few hundred of A for in-plane STT and tens of A for perpendicular STT memory cells. While the first generation Oersted field based MRAM technologies needed large cross-point transistors precluding their scalability beyond 90 nm, the STT devices with lower Write current can be scaled in the regime of 28 nm or so. However, in order to advance the frontier of semiconductor based magnetic memories, the Write current of the memory device should be tailored to a few hundreds of nA. The tutorial will specifically emphasize on emerging Straintronics RAM devices comprising an alloy of lead-zirconate-titanate (PZT) and Galfenol/Terfenol/Cobalt/Nickle (magnetostrictive) layers and will demonstrate how by combining both piezoelectricity (in PZT layer) and Villari effect (in magenteostrictive free layer), the Write current can be reduced by over two orders of magnitude. Specifically, the tutorial will provide the detailed analysis of the energy barrier of magnetostrictive free layer, and then explain the mathematical framework of the 3-D modeling technique that has been developed to model the behavior of magnetization damping along the hard axis of the elliptical free layer. In addition to the physics based models, the tutorial will discuss how to build Verilog-A models of the above-mentioned spintronics and straintronics devices. Finally, the tutorial will discuss a few applications of spin based devices in non-volatile digital memories, neuromorphic circuits for image processing, and associative memories consisting of Spin Torque Nano Oscillators (STNOs). |
T13: Compressive Sensing: Theory, Design, and Applications – CANCELLED |
This tutorial has been cancelled. Apologies for any inconvenience caused.Facilitator/s: Yehia MassoudCompressive sensing provides a framework for overcoming many of the bottlenecks stemming from the Nyquist sampling theorem and the resulting entanglement of system bandwidth and power consumption. By allowing the recovery of a wide range of signals from sub-Nyquist samples, compressive sensing provides a powerful tool for highly reducing the power consumption in communication and sensing systems and provides solutions in a wide range of areas from biomedical instrumentation to modern communication systems.This tutorial presents a comprehensive coverage of a topic of ever-increasing importance to the Circuits and Systems community; compressive sensing. This tutorial will give a holistic view of compressive sensing, from theory to implementation, the mathematical and signal processing foundation for compressive sensing and the design process for the realization of efficient compressive sensing systems. The tutorial will give an introduction on the theory of compressive sensing and some of the challenges facing the implementation of compressive sensing-based systems. Compressive sensing systems differ in many aspects from traditional communication and sensing systems and require new design techniques that bridge the theory of compressive sensing to efficient hardware realizations. This tutorial will show how the theoretical concepts translate into specifications at the circuit level and how efficient and accurate hardware models are necessary in the domain of compressive sensing. The tutorial will show how combining these design techniques and hardware models can mitigate the challenges facing the realization of compressive sensing systems. We also introduce new architectures and techniques for the realization of compressive sensing systems and ubiquitous/reconfigurable receivers for modern communication systems. In addition, the tutorial will also provide a comprehensive overview of the applications of compressive sensing in different field such data acquisition and compression, image processing, biomedical applications, low power design and wireless and communication systems. |
T14: Neuromorphic Systems: Towards Deep Submicron and Real World Applications |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 211 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Christian MayrNeuromorphics denotes a scienti_c discipline that deals with the VLSI implementations of information processing inspired by neural systems. Starting with small-scale, dedicated ICs in a few labs in the late 90′s, these systems have now signi_cantly grown in size and processing power and are researched by various groups from academia as well as recently also by private industry. The IRS roadmap is also looking towards neuromorphics as a possible paradigm for future highly-parallel and nanoscale VLSI approaches that can handle unreliable devices.In terms of hardware, there is a wide range of neuromorphic systems available now or in the near future, from fully analog realizations to mixed signal, custom digital or nanoscale arrays. In terms of computational paradigms, there has been a shift in the neuromorphic community from the early focus on reengineering the brain towards a wider approach of using the computational primitives of the brain for general information processing. Several neuroscience groups have pre- sented approaches that can leverage the computational power offered by current neuromorphic systems for a wide variety of processing tasks.This tutorial looks at large scale/deep submicron/nanoscale neuromorphics in academia as well as in industry to answer four questions: (i) What is the current state of development and future roadmap, (ii) what are the tradeoffs between the different hardware approaches, (iii) what computational paradigms can be run on these systems that would interest the general VLSI and computer science community, (iv) and what kind of user interfaces are being developed to facilitate adoption of these systems into the general community. Paying tribute to the trend towards VLSI Systems-on-Chip (SoC), the tutorial also outlines how neuromorphic processing cores (mixed-signal and digital) may be integrated into existing SoCs and how SoCs might leverage this additional processing capability. |
T15: Switching Noise Reduction Techniques in DC-DC Converters for Powering Noise-Sensitive Analog and RF Loads |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 216 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Ayman FayedMobile communication and navigation devices have fueled the demand for low power implementations to enhance battery life. A critical aspect of that is the efficiency of the process of converting power from the battery to the various loads in the system. However, the large noise-sensitive analog/RF content in these devices is limiting the use of efficient DC-DC switching power converters due to the large switching noise associated with such converters, which degrades the performance of analog/RF loads. This forces the use of inefficient, but lownoise power converters, such as linear regulators, along with large passive components for noise suppression. Unfortunately, this reduces battery life and increases implementation cost. This tutorial will start with introducing the basic operation of DC-DC power converters and the relationship between their various design parameters and the switching noise they produce. This will be followed by a discussion of the various mechanisms with which this switching noise can impact the operation of analog/RF loads, such as RF power amplifiers, either directly through powering of these loads, or indirectly through coupling through shared power pins and silicon substrate. An in depth analysis of the spectral behavior of the switching noise produced by DCDC converters with various control techniques such as PWM and PFM control during DCM and CCM operation modes will then be introduced, followed by an overview of the most common switching noise reduction techniques in DC-DC converters and a discussion of advantages and shortcomings of each technique. This includes active ripple cancellation, multi-phase converters, delta-sigma control, and frequency hopping/stepping. The tutorial will then focus on new analog/RF friendly control techniques that eliminate the inherent periodic switching noise in DCDC converters leading to a completely spur-free noise spectrum at all nodes in these converters. These techniques enable powering analog/RF loads directly from DC-DC converters, better SoC integration, effective power supply rail sharing, and significant reduction in EMI. |
T16: Class-D: Fundamentals, Design tradeoffs and Open problems |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 216 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Edgar Sanchez-Sinencio, Joseph Chang and Ge TongAudio Class-D amplifiers are increasingly ubiquitous – In 2012, the market for Class D audio amplifiers exceeded 2 billion units, including their embodiment in smartphones, tablets, TVs, etc. This is mainly because of because of their high power-efficiencies (~90% at high modulation indexes (signal swing)). It is well known that there is a real need for Class D amplifiers whose fidelity and noise immunity (particularly for GSM/CDMA smartphones) specifications are substantially higher than what is available today – ‘Ultra High-Quality’ amplifiers whose unprecedented specifications include THD+N<-100dB and PSRR>100dB. At this juncture, despite the ubiquity of Class D amplifiers and the need for Ultra High-Quality Class D amplifiers, they are unavailable as COTS and remain unreported in literature. Interestingly, recent research indicates that Ultra High-Quality Class D amplifiers are not attainable unless power-efficiency and EMI are compromised.In this tutorial, we will provide a comprehensive review of analog Class-D amplifiers with emphases towards power-efficiency and the ensuing trade-offs between power-efficiency and nonlinearities, particularly fidelity and noise-immunity. Unlike linear amplifiers, the phenomena of nonlinearities in Class D amplifiers are generally not well appreciated – the nonlinearities include nonlinearities analogous to that in linear amplifiers and that unique to Class-D amplifiers. In the tradeoff, some well-accepted approaches to mitigate nonlinearities have the surprising effect of being the converse. We will also present various commonly used modulation schemes in analog Class D amplifiers and compare the performance of these modulation schemes with emphasis on high power-efficiency, high fidelity and high noise-immunity. Design methodologies towards Ultra High-Quality for various modulation schemes will be presented. We will also present the optimization of the output stage of Class D amplifiers for high power-efficiency.Overall, this tutorial serves to provide useful insight to Class-D amplifier designs. |
T17: Small Scale Energy Harvesting (EH) – Principles, Practices,and Future Trends |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 213 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Dong HaHarvesting small scale energy from otherwise wasted ambient energy sources has attracted immense research efforts for applications such as battery-powered wireless sensor networks, industrial condition monitoring, and healthcare. The power level for those applications ranges from a few microwatts to hundreds of milliwatts. Energy scavenged from ambient sources may be able to recharge or even replace the battery to power up those devices perpetually. Sources of energy for harvesting include, but are not limited to, light, thermal gradient, vibration, air flow, and radio frequency radiation. The fluctuation and intermittence of these ambient energy sources combined with a small amount of available energy pose severe technical challenges to develop practical self-powered systems. Further, energy storage devices like rechargeable batteries or supercapacitors as well as efficient power management circuits are indispensable to convert a dynamic environmental energy input into a stable power source. This tutorial reviews principles of energy harvesting, practices for small scale energy harvesters, including energy harvesters and integrated circuits developed recently in industry and academia. The industry trends and possible research issues for power management circuits are also discussed to provide a technical insight into energy harvesting techniques and their applications. |
T18: Near‐field wireless power and data telemetry |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 213 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Wang GuoxingWireless power and data transmission continues to be an important issue for many applications, such as sensor network, implantable electronics, internet of things, etc. Inductive link (near‐field) remains the most widely used technology if the transmitter and receiver can remain close proximity. In bio‐related applications, such as retinal prosthesis, brain‐machine interfaces, challenges exist with regard to improving efficiency of power transmission and increasing data rate while maintaining power consumption level low. In recent years, researchers have been exploring new circuits and new architectures to overcome the challenges and improve the efficiencies. In this tutorial, the building blocks of the near‐field transmission will be covered, including power amplifiers, coils, power receivers, data modulators, and data demodulators. Special attention will be paid to the design and optimization of coils. Architectural tradeoffs for a systematic optimization will be discussed with examples given. Recent development on wireless power and data telemetry technologies will be summarized and future research directions will be discussed. |
T19:Interfacing Organisations: How to successfully manage organisational interfaces |
Time: 13:30 – 16:30 Venue: Melbourne Convention Centre Room: 218 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Felix LustenbergerIn today’s globally operating world of business and academia, no single person can achieve far-reaching goals in his/her own. We are always part of a larger network. In order to improve the quality as well as the quantity of useful results we inevitably have to cooperate and work together at group, department, company or even inter-company/organization level. In many cases, the individual sub-organizations are distributed globally over time zones and cultures. This increases the complexity of managing such large and diverse organizations even more. As an individual you are always either managing other people or you are being managed by some superior entity in hierarchy. In either situation it is beneficial to understand the mechanisms of interaction and play the management instruments for seamless organizational interfaces.The goal of this half-day tutorial is to make you as a practicing engineering manager or engineer aspiring to a management position in the future aware of the various organizational interfaces and present potential approaches to solve (inter-) organizational issues and pitfalls arising from geographical, cultural, age-related and other elements. The tutorial is not meant to provide final recipes for each and every practical problem but rather to stimulate the thinking on this topic and provide basic approaches. The oral presentation will be alternating with discussions of practical examples and approaches. Input from the audience will be very welcome and will enrich the experience and value for all attendees.For the presentation of practical examples, the instructor will mainly tap into his personal experience he has acquired over the almost 20 years in academia, start-ups and larger business organizations. He is also in charge of the portfolio on the same topic that appears regularly in the IEEE Engineering Management Review, which was the starting point for this tutorial. |
T20: Managing Technology Professionals: Transitioning from Individual Contributor to Management |
Time: 9:00 – 12:00 Venue: Melbourne Convention Centre Room: 218 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Tuna B. TarimCan technical professionals easily transition to becoming effective engineering and technology managers? Many technical professionals believe that the answer is “yes.” Comments like the following are not uncommon: “I’ve led projects and always got along well with the project team; I’ll make a good manager,” or “I’ve been working in this company for so long, and I know a lot of people,” implying that knowing people is enough to manage their activities. Others might say, “I know the technology and I’ve done very well as an individual contributor, so now, I would like to become a manager.” Many people think about the technical aspects of managing, but tend to disregard the professional aspects. Too often, even the most seasoned managers fail to understand that the manager needs to lead and manage their team, both technically and professionally, work with their team members on their personal development to make them the best technical contributors they can be, give them technical and professional advice and career guidance, and appoint the candidate who meets the job requirements.The goal of this half-day tutorial is to give an understanding of all aspects of management to the practicing engineer, engineering manager and those who aspire to become managers so that the individuals can make an assessment regarding whether this is a career choice they wish to make. The goal is to make this an interactive tutorial where attendees can share their experiences and comment on the experiences of each other. The instructor will share her own experience on various aspects of management, which she also shares in quarterly articles in the IEEE Engineering Management Review. |
T21: If it’s Pinched it’s a memristor |
Time: 9:00 – 12:00 (Chua 09:00 – 10:30) Venue: Melbourne Convention Centre Room: 208 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Leon ChuaFirst built by hp in 2008, the memristor has now been identified in many unrelated disciplines ranging from brain science to botany. They all share the unique fingerprint of a “pinched hysteresis loop”.This talk reviews the circuit and system theoretic concepts essential for an in-depth understanding of the memristor and clarifies some misconceptions among the uninitiated. |
T22: ReRAM Memristive Devices: Electrochemical Systems at the Atomic Scale |
Time: 9:00 – 12:00 (Valov 10:50 – 12:00) Venue: Melbourne Convention Centre Room: 208 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Ilia ValovControl over physicochemical processes at the atomic scale is the key factor for development of the future nanoelectronics and information technology fulfilling the demands for low power consumption, high information density, fast read and write speeds and non-volatility. In that respect, major candidates for the next generation memory devices are the redox ReRAM cells. Based on a simple Metal-Insulator-Metal structure these type memories also demonstrate great promise as building units for memrisitve and neuromorphic operations, paving the way for beyond von Neumann computing.The present talk will focus on the thermodynamics and kinetics of nanoscaled memristive devices emphasizing the ability to control the device processes at the atomic scale. The interface dynamics, the importance of local charge concentration and distribution, and the generic relevance of the counter charges will be highlighted. The nanobattery effect and its implications on both memristors’ theory and device stability and performance will be discussed on theoretical and experimental level. In this context strategies for improving the memristive devices will be pointed out. |
T23: Analog and Mixed-Signal Applications of Memristive Devices |
Time: 13:30 – 16:30 (Strukov 13:30 – 15:00) Venue: Melbourne Convention Centre Room: 208 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Dmitri StrukovResistive (“memristive”) switching in thin films has many prospective applications in computing with the majority of the proposed applications are in digital domain, e.g. in digital memories and reconfigurable digital logic. A very exciting aspect of resistive switching is that very often it is a well-controlled continuous process, allowing for practical implementation of analog memory, which is useful for analog computing. There are already many proposals and even experimental demonstrations of simple circuits taking advantage of analog properties of memristive devices, e.g. to implement tunable gain in operating amplifiers, analog memory, analog and mixed-signal dot-product operation, which can be utilized to implement linear threshold gates, conversion circuits, and neuromorphic circuits. In my talk I will review recent experimental and theoretical efforts on analog computing with memristive circuits. |
T24: Integrating memristive devices in CMOS neuromorphic computing architectures |
Time: 13:30 – 16:30 (Indiveri 15:20 – 16:30) Venue: Melbourne Convention Centre Room: 208 Cost: Included in full symposium registration fee $AUD180.00 inc GST for tutorial only (no full symposium registration) Facilitator/s: Giacomo IndiveriFor many practical tasks, conventional computing systems cannot match the performance of biological systems. One of the reasons is that the architecture of nervous systems, in which billions of nerve cells communicate with action potentials (so called “spikes”) in parallel, is very different from that of today’s computers. Recently developed brain-inspired hardware architectures that emulate the biophysics of real neurons and synapses represent a promising technology for implementing alternative computing paradigms. Memristive devices are a key element of this technology.In this presentation I will present an overview of past and present neuro-computing approaches, and outline hybrid analog/digital circuits that can be interfaced to memristive devices for directly emulating the dynamics and computational properties of biological neural processing systems. |
